In data communications systems, data is often transmitted between devices via a parallel data bus. The number of lines connecting the devices is determined by the number of data bits, N, in the parallel bus. Additional control signals, such as transmit data strobe and receive data strobe may be required and may also require separate lines in the parallel data bus. However, for simplicity, it will be assumed that the number of lines in the parallel data bus is equal to the number of data bits, N.
The rate at which the data is transmitted (information rate), is given by the number of lines, N, multiplied by the number of times per second new information can be applied to the bus (bus word rate). Therefore, the information rate is given by (N) X (bus word rate).
In a controlled environment in which distance between devices is limited, such as on an integrated circuit (IC) chip or printed circuit (PC) board, each line can normally be switched at a much higher rate than the bus word rate. Increasing the switching rate results in a corresponding increase in the information rate. However, increasing the switching rate for all N lines in the parallel bus concomitantly increases the amount of power that must be dissipated in the IC chip or PC board. This increased power dissipation could cause internal circuit elements to fail. In addition, an increased switching rate also increases the amount of electromagnetic interference (EMI) or noise induced on other components in the circuit. EMI associated with switching multiple pins simultaneously could cause a circuit to misoperate and transmit faulty data onto the bus.
FIG. 1 shows a conventional digital data communication system utilizing an N bit parallel data bus, in this example an eight bit bus which requires eight individual wires to interconnect functional blocks 12, 14 and 16. Alternatively, the N-bit bus may be 16 bits in width, 32 bits or any other number that a particular system may utilize. However, the wider the data bus is, the number of wires needed to interconnect functional blocks 12, 14 and 16 is greater.
Attempting to increase information rate by increasing the width of the data bus adds to hardware requirements by increasing the number of lines in the parallel data bus. Correspondingly, this also increases the number of IC pins required to input and output the data between the functional blocks. In addition, as noted above, attempting to increase the information rate by increasing the rate at which data is switched on the parallel bus results in increased power dissipation and EMI on the components in the circuit.
In view of the above, a need exists for increasing the information rate of data being transferred between devices while keeping the amount of noise and power dissipation to a minimum. It additionally is desirable to increase the information rate while maintaining accurate, regulated data transmissions.